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// agreement for further details.
		
module level_signal_sync2
#(
parameter   DEFAULT_VALUE = 0
)
(
input   des_clk,
input   des_rst_n,
input   data_in,

output  data_out

);

reg     data_out_r1;
reg     data_out_r2;

always @(posedge des_clk or negedge des_rst_n) begin
   if(!des_rst_n) begin
	   data_out_r1    <=  DEFAULT_VALUE;
	   data_out_r2    <=  DEFAULT_VALUE;	
	end
	else begin
	   data_out_r1    <=  data_in;
		data_out_r2    <=  data_out_r1;
	end
end

assign data_out       =  data_out_r2;

endmodule
